The present invention relates in general to semiconductor chip packages. More specifically, the present invention relates to fabrication methods and resulting structures for a semiconductor chip package having a mixed under-bump metallization (UBM) size and pitch on a single die.
A semiconductor chip, also commonly referred to as an integrated circuit (IC) chip or a die is typically assembled into a semiconductor chip package that is soldered to a printed circuit board. One type of semiconductor chip package is a flip chip, also known as a controlled collapse chip connection (“C4”) package. The semiconductor chip package typically includes the IC chip, which contains a number of round solder bumps that are attached to a top surface of the chip. The IC chip, via the solder bumps, is soldered to solder pads located along a surface of a package substrate, forming a metallurgical joint between the chip and the substrate. On package I/O (OPIO), optics, and dual chip modules (DCM) are becoming key components for enabling next generation semiconductor chip packaging, especially for server systems. These next generation packages include under-bump metallization (UBM) stacks that provide an electrical connection from the die to the solder bump. UBM stacks, also referred to as C4s, include one or more stacked metallization layers. C4s carry electrical current between the semiconductor chip and the substrate.